1. Technical Field
The present invention relates to a semiconductor device having a field-effect transistor and to a method for manufacturing the same.
2. Description of Related Art
An ultra-integration silicon circuit is one of the basic technologies that are expected to support a future advanced information society. Higher functionality of an integrated circuit entails higher performance of semiconductor elements which are constituent elements of the integrated circuit; namely, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a CMOSFET (Complementary MOSFET), and the like. Higher performance of the element has been basically achieved according to a proportional scaling rule. However, various limitations on physical properties have recently come to pose difficulty in ultra-miniaturization of an element which contribute to higher performance.
For instance, problems are pointed out in connection with a gate electrode using silicon; namely, manifestation of gate parasitic resistance caused by an increase in the operating speed of an element; an reduction in the effective capacitance of an insulation film attributable to depletion of carriers in an interface of the insulation film; and variations in a threshold voltage attributable to punch-through of impurity additives into a channel region. In order to solve these problems, metal gate materials are proposed.
One of the techniques for forming a metal gate electrode is a full silicide gate electrode technique for silicidizing all gate electrodes with Ni or Co. The metal gate electrode requires a work function which varies according to a conductivity type, in order to operate a device at an optimal operation threshold voltage.
The reason for this is that the operation threshold voltage of the MIS transistor is modulated in accordance with variations in the work function (Φeff: an effective work function) of the gate electrode in the interface between the gate electrode and the gate insulation film. Consequently, variations in the work function of the gate electrode in the vicinity of the interface appear in unmodified form as variations in the operation threshold voltage.
For instance, an attempt has been made to control the work function by adjusting the composition of silicide or a crystalline structure (Please refer K. Takahashi et al., “Dual Workfunction Ni-Silicide/HfSiON Gate Stacks by Phase-Controlled Full-Silicidation (PC-FUSI) Technique for 45 nm-node LSTP and LOP Devices,” IEDM 2004, 4.4.1-4.4.4 (hereinafter, referred to as “K. Takahashi et al.”), and N. Biswas et al., “Workfunction turning of nickel silicide by co-sputtering nickel and silicon,” Applied Physics Letters 87, 171908 (2005) “hereinafter referred to as N. Biswas et al.”).
“K. Takahashi et al” discloses that a work function pertaining to the composition of NiSi2 lies in the vicinity of about 4.4 eV and is appropriate for NMOS metal and that a work function pertaining to the composition of Ni3Si lies in the vicinity of about 4.8 eV and is appropriate for PMOS metal. Consequently, these gate electrodes involving composition control show that the effective work function Φeff varies by about 0.1 eV, which in turn induces variations in the threshold voltage. This is considered to be attributable to the fact that the crystal phase of the gate electrode is not a single phase but a mixed phase. Therefore, a single crystal phase is desired for controlling a work function.
In “K. Takahashi et al”, an attempt is made to induce a solid phase reaction in the interface between an Ni layer/a polycrystalline Si layer by varying a thickness ratio of an Ni layer/a polycrystalline Si layer (a composition ratio of NiSi) and a heat treatment temperature (ranging from 350° C. to 650° C.). The document describes that a mixed phase between the NiSi phase and an Ni3Si phase, a mixed phase between the Ni3Si phase and an Ni31Si12 phase, and a mixed phase between the NiSi phase and the NiSi2 phase are consequently generated. However, for instance, when a single phase; e.g., an NiSi2phase, is formed, heat treatment at 650° C. or more is required. When silicidation is performed at such a high heat treatment temperature, the gate insulation film is deteriorated, which in turn leads to an increase in a leakage current.
In JP-A-20005-129551, an attempt is made to change the ratio of the thickness of the Ni layer to the thickness of the polycrystalline Si layer, and to subject the layers to heat treatment at 400° C. in a vacuum for one minute, thereby inducing a solid-phase reaction in the interface between the Ni layer and the polycrystalline Si layer. The resultantly-produced (Ni+Si) layer exhibits a work function from about 4.4 eV to about 4.9 eV. However, the layer is considered to be a mixed phase consisting of Ni, Si and various species of NiSix, and the work function is expected to vary.
K. Takahashi et al. discloses that a work function from about 4.3 eV to about 4.9 eV is exhibited when the silicide composition of NiSix is varied. However, various crystal phases are observed from the result of XRD (X-Ray Diffraction) of NiSix, and a mixed phase is understood to be formed.
Forming Ni silicide having a single-phase crystal structure is difficult. Therefore, variations in threshold value cannot be diminished. Moreover, even when Ni silicide having a single-phase crystal structure can be formed, a silicide reaction induced by high-temperature heat treatment is required, as in the case of the NiSi2 phase, which in turn causes an increase in leakage current. Consequently, Ni silicide of single phase cannot be used for gate electrodes of both conductivity types (particularly type “n”).
A known approach is to silicidize single crystal Si and amorphous Si by low-temperature heat treatment at 350° C. to 400° C., thereby generating NiSi2 (see O. Nakatsuka et al., “Low-Temperature Formation of Epitaxial NiSi2 Layers with Solid-Phase Reaction in Ni/Ti/Si (001) Systems,” Japanese Journal of Applied Physics, Vol. 44, No. 5A, 2005, pp. 2945-2947 (hereinafter, referred to as “O. Nakatsuka et al.”), and C. Hayzelder et al., “Silicide formation and silicide-mediated crystallization of nickel-implanted amorphous silicon thin films,” J. Appl. Physics. 73(12), 15 Jun. 1993, pp. 8279-8289. )(herein after referred to as “C. Hayzelder et al.”).
“O. Nakatsuka et al.” discloses that a multilayer consisting of Ni, a thin layer of Ti, and monocrystal Si is subjected to heat treatment at 350° C. for 30 minutes, to thus produce a multilayer structure consisting of TiSi2, NiSi2, and monocrystal Si. However, an interface between NiSi2/monocrystal Si forms a (111) facet, which in turn induces roughness.
“C. Hayzelder et al.” discloses that Ni is ion-implanted into amorphous Si and the amorphous Si is subjected to heat treatment at 400° C. for three hours, to thus generate an NiSi2 crystal seed. However, heat treatment which is as long as three hours is not realistic in processes for manufacturing an LSI.